A flawless design depends on a flawless verification plan. For the first time, you will know if your functional verification plan is flawless! Our breakthrough technology assures it by looking exhaustively outside the verification plan. It is surprisingly easy to use and surprisingly fast with wonderful scalability.

Will your verification work catch all functional bugs that you want to catch? If your verification plan developers answered this question only by brainstorming and peer reviewing but you want a surer answer, you need our new technological solution.

Our solution is to be used early in your verification project. It tells you whether the completion of your planned work will possibly miss bugs of interests to you. It either conclusively approves your plan or suggests new corner tests with solid reasons presented in an automatically generated Verilog test bench.

A part of your plan might be already perfect but you probably still try to add tests to it. Given all the tools that you use to code and run tests, the only gap between you and the complete success is probably just the conclusive approval from our solution.

If you have more work than the budget allows, you probably can identify redundant tests in your plan with our solution. If the budget is flexible, you can probably see for the first time what it takes to catch all functional bugs.

Our solution fits well into any verification flow that can generate waveforms in VCD format and where all RTL code is in Verilog. It works smoothly with directed tests, randomized tests and even formal property checking. It complements coverage-driven verification because it only determines whether reaching the coverage goals can assure catching all bugs. It is the job of coverage-driven verification or any other verification flow (including hardware-based ones) to assure reaching the coverage goals.

Our solution does not require any coding or drawing. It provides choices in its GUI for users to identify, on a key section in the waveforms for a test, both the related bug-catching need according to the functional specification and the related bug-catching power according to the verification plan. Then the GUI automatically generates a Verilog model, and this model's structure is shown in the diagram below, where 2 halves of the diagram represent respectively the bug-catching power and the bug-catching need.

The principle behind our solution is related to running similar tests. If 2 tests are proven to generate the same response and they are expected so, 1 of them is not needed at all.

Our solution runs surprisingly fast. It is in a way similar to various formal verification tools, but it does what no other tools can. Other tools cannot be used to conclusively approve coverage goals. If your verification plan has flaws due to the high cost to catch certain unlikely but critical bugs, you do not have to take the risk any more.

Our solution removes flaws from verification plans. Perfect verification plans lead to catching all functional bugs in designs. Perfect verification plans also can reduce verification costs.

Among our successes, We are able to prove that there is no need to use 2-way traffic in verifying the transmission correctness of a full-duplex Ethernet design that has multiple clocks.

Key benefits:

• Improving functional verification efficiency dramatically in planning, coding, runtime and debugging
• Making it practical to catch all serious functional bugs in logic designs with most existing verification flows
• Catching negligence in functional verification plans and in functional specifications
• Enabling better budget/schedule estimates and prioritization flexibilities
• Clarifying return on investment (ROI) of verification tasks
• Supporting better optimized use of multiple functional verification technologies in the same project

Key features:

• Working with any existing verification flow without introducing coverage overlap
• Supporting all verification languages in existing flows
• Massively (with test counts in many thousand digits or more) identifying absolutely redundant tests (as results of planned tests) outside the verification plan
• Automatically generating tests in Verilog to suggest verification plan enhancements
• Using any debugging environment for Verilog
• Associating each failing test with a similar passing test for quick trouble shooting
• Requiring no coding/drawing except Verilog (gate level or RTL) DUT and waveforms in VCD
• Getting details of design intent, of functional specification and of verification plan from GUI interaction and waveforms in VCD
• Scaling well for large designs and for huge sets of tests
• Reaching conclusions on sections of verification plans normally with runtime in minutes rather than hours
• Exhaustively verifying selected features fast with the old flow and allowing any changes of the selection at any time during a project without wasted effort

Publications:

• J. Li, "Automated risk elimination by formally critiquing verification plan and design documentation" DesignCon, Santa Clara, February 7, 2006.
• J. Li and C. Meas, " Embedding formal techniques to direct test suites: a path to rapid exhaustive functional verification" DVCon, San Jose, February 23, 2006.

How to get more information?

Copyright © 2005 Superior Logic Corporation